1. Field of the Invention
The present invention relates to high voltage integrated circuits.
2. Description of Related Art
Some integrated circuits require high voltage transistors. For example 3D flash memory devices have been developed that can require circuits to apply high magnitude voltages during program and erase operations. For example, the maximum operation voltage for word lines can be about 22 to 24V for most NAND Flash memories. The large maximum programming voltage is to ensure slow cells can be correctly programmed to the maximum high threshold state, where for multilevel cells the verify voltage corresponding to the maximum high threshold state is higher than Vt=3V. In order to allow 24V to pass through a high voltage NMOS device to a word line, the gate voltage must provide sufficient gate over drive to allow easy pass through of the word line voltage. The necessary gate voltage (Vpp) can be 5V higher than the word line voltage, leading to a gate voltage requirement of greater than 29V. The large gate over drive is to compensate body effect phenomenon the source of the NMOS is raised to the word line voltage. So a voltage path is needed that can support very high junction breakdown voltages.
High voltage CMOS transistors have been deployed for these purposes, which can require significant layout area on the chip. A representative high-voltage MOSFET used in NAND flash memory can require planar transistor with the channel width of about 2μ, a channel length of about 1.2μ, spacing for offset between gate polysilicon and n+ source/drain terminals of the transistor more than 0.6μ, and shallow trench isolation STI structures having widths on the order one micron. If the channel width is too small, breakdown degradation is experienced. The n+ source/drain junction can be affected by the corner of the STI structure. As a result, the semiconductor on the edge of the structure is often implemented with a heavier P-type doping to avoid parasitic sidewall turn on leakage. Additional space is required between the source/drain terminals and the STI structure because of the heavier p-type doping along the edge. The spacing between the STI structures is limited by the field isolation requirement. For NAND flash with the 25 V programming bias, the STI spacing needs to sustain the difference between the program voltage on one word line and the pass voltage on an adjacent word line, which can be on the order of 15 V. The channel length is limited by high voltages punch through requirements. A drain offset between the source/drain terminal and the polysilicon gate has to be implemented to suppress gate induced drain leakage and gate breakdown.
All of these spacing requirements contribute to a very large layout requirement for high-voltage circuits of this type designed to operate at 30 Volts or more on an integrated circuit. In a representative implementation, a planar high-voltage CMOS circuit can require a 3μ, pitch (device to device spacing) for layout of high-voltage transistors designed for breakdown potentials greater than 30 V.
Also, 3D memory often has large word line resistance/capacitance RC delay. As a result, such devices can require more partitions of the memory array on the chip to reduce the size of individual word lines. High voltage drivers are needed for each of the partitions. As a result, the CMOS word line driver area can consume a very significant part of the die size.
It is desirable to provide high voltage circuits suitable for use in 3D memory and other high voltage integrated circuits that reduce the total layout area required without sacrificing performance and reliability.